1. Field of the Invention
The present invention is in the field of electrostatic discharge (ESD) protection for integrated circuits. More particularly, the present invention is in the field of electrostatic discharge protection for a metal oxide semiconductor (MOS) integrated circuit.
2. Related Technology
A conventional integrated circuit with punch through electrostatic discharge protection is seen in U.S. Pat. No. 4,734,752, issued 29 Mar. 1988, to Y. Liu, et al. The '752 patent is believed to disclose an electrostatic discharge protection structure in which a FET is provided, and which operates in a punch through mode. The FET is of conventional construction.
Another conventional integrated circuit electrostatic discharge protection structure is seen in U.S. Pat. No. 4,987,465, issued 22 Jan. 1991, to S. Longcor, et al., in which a pair of clamping structures cooperate to conduct ESD currents to ground. The clamping structures may be a lateral bipolar transistor, a MOS device, or a MOS device with a ballast resistor. The required structures for this ESD scheme appear complex, and would probably be expensive to produce in practice.
Still another ESD protection structure is seen in U.S. Pat. No. 5,027,252, issued 25 Jun. 1991, to R. Yamamira. This patent is believed to teach an ESD structure in which a pair of transistors in punch through mode are arranged with a first of these transistors having its gate terminal connected to an input pad of the device, and the second of these transistors has its gate terminal at ground potential of the device. Again, the structure necessary to realize this ESD scheme is quite complex, and expensive.
U.S. Pat. No. 4,739,378, is believed to teach an ESD scheme in which a pair of zener junctions are buried beneath a pad of the circuit device. The zeners are arrange in opposite polarity direction between the pad and ground, and are created by buried doping layers including a layer of one dopant type and a pair of vertically extending doping regions of opposite dopant type extending downwardly from the pad to the buried dopant layer, and forming the zener junctions.
Yet another ESD structure is seen in U.S. Pat. No. 5,162,966, issued 10 Nov. 1992, to T. Fujhira. This patent is believed to teach a circuit structure in which a zener diode is formed and connected to the gate of a lateral FET to switch this FET in the event of a ESD event so that surge current from the event is conducted to ground via the zener and FET.
U.S. Pat. No. 5,173,755, issued 22 Dec. 1992, is believed to teach an ESD structure in which a capacitively coupled zener diode is connected to a lateral bipolar transistor formed in a thick oxide film of the circuit device. The conduction of charge past the zener during an ESD event switches on the lateral bipolar, so that surge current from the ESD event is conducted to ground.
Still another ESD device is taught by U.S. Pat. No. 5,223,737, issued 29 Jun. 1993, in which a zener diode is believed to provide a base bias to a lateral bipolar transistor. The current conduction of the zener during an ESD event switches on the transistor so that ESD surge current is conducted to ground.
U.S. Pat. No. 5,017,985, issued 21 May 1991 is believed to show an ESD structure in which an insulated gate FET provides a conductive path to ground in the event of an ESD to a contact pad of the device.
Also, U.S. Pat. No. 4,855,620, issued 8 Aug. 1989, is believed to teach an ESD protection structure in which an FET is embedded in the field oxide of a circuit device, and is switched on during a ESD event to shunt surge current to ground, or to a controlled voltage source.
Many of the ESD schemes and structures discussed above are complex, and expensive to manufacture. Many of these ESD circuits rely on the cooperation of several circuit elements to achieve their desired result, and are influenced in the level or degree of protection which they provide by variations in the values of the various components of the ESD circuit.